1. Field of the Invention
The present invention relates to a silicon-on-insulator (SOI) substrate. Further, the present invention relates to a semiconductor device which is manufactured using the SOI substrate.
2. Description of the Related Art
In recent years, an integrated circuit using an SOI (silicon on insulator) substrate in which a thin single crystal semiconductor layer is formed on an insulating surface, instead of a bulk silicon wafer has been developed. Since parasitic capacitance between a drain of a transistor and a substrate is reduced with the use of an SOI substrate, an SOI substrate has been attracted attention as one improving performance of a semiconductor integrated circuit.
A Smart Cut (registered trademark) method is known as one of methods for manufacturing an SOI substrate. An outline of the method for manufacturing an SOI substrate by a Smart Cut (registered trademark) method is described below. First, hydrogen ions are implanted into a silicon wafer by an ion implantation method, so that an ion implantation layer is formed at a predetermined depth from a surface. Then, the silicon wafer into which the hydrogen ions are implanted is bonded to another silicon wafer with a silicon oxide film interposed therebetween. After that, the ion implanted layer is to be a cleavage plane by heat treatment, and the silicon wafer into which the hydrogen ions are implanted is separated in a thin film state, so that a silicon film is formed on the bonded silicon wafer. A Smart Cut (registered trademark) method may be referred to as a hydrogen ion implantation separation method.
As the hydrogen ion implantation separation method is a method in which ions are separated by mass, ions are deflected electromagnetically, and then ions are implanted to a fixed substrate by performing a raster scanning, there is a variation in a distribution of ion implantation of concentration of ions or a depth at which ions are added, so that projections and depressions are generated on a surface of a single crystal semiconductor layer which has been cleaved. When there are large projections and depressions on a surface of the single crystal semiconductor layer and a gate insulating film is formed thereover, the projections and depressions penetrate the gate insulating film, which causes a problem of leakage between the semiconductor layer and a gate electrode.
Therefore, in general, chemical mechanical polishing (CMP) is performed on the surface of the semiconductor layer having the projections and depressions after cleavage Reference 1 (Japanese Published Patent Application No. H11-307472) discloses a technique in which a surface of a single crystal semiconductor layer is planarized by heat treatment in a hydrogen atmosphere after the cleavage.
As an example of a technique of forming a thin single crystal silicon film over a glass substrate by such a Smart Cut (registered trademark) method, a technique by the present applicant has been known (for example, Reference 2: Japanese Published Patent Application No. H11-163363).